46 lines
850 B
Verilog
46 lines
850 B
Verilog
module top;
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reg passed = 1'b1;
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reg signed [15:0] a, b;
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/* Currently the result can only be as big as a native long! */
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wire signed [31:0] r = a ** b;
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initial begin
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a = 5;
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b = 2;
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#1
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if (r != 25) begin
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$display("Failed: 5 ** 2 gave %d, expected 25", r);
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passed = 1'b0;
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end
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a = -5;
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b = 3;
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#1
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if (r != -125) begin
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$display("Failed: -5 ** 3 gave %d, expected -125", r);
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passed = 1'b0;
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end
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a = 2;
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b = 30;
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#1
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if (r != 1_073_741_824) begin
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$display("Failed: 2 ** 30 gave %d, expected 1,073,741,824", r);
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passed = 1'b0;
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end
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a = -2;
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b = 31;
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#1
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if (r != -2_147_483_648) begin
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$display("Failed: -2 ** 31 gave %d, expected -2,147,483,648", r);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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