18 lines
362 B
Verilog
18 lines
362 B
Verilog
// Check that $signed/$unsigned works when being combinatorially assigned with a
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// delay and the target of the function is a net without any drivers.
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module top ();
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wire [7:0] a;
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wire signed [7:0] b;
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assign #1 b = $signed(a);
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initial begin
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#10
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if (b === 8'hzz) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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