23 lines
413 B
Verilog
23 lines
413 B
Verilog
// This is just a syntax test.
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/* comment */ `resetall /* comment */ // comment
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/* comment */ `celldefine /* comment */ // comment
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module cell1;
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endmodule
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/* comment */ `endcelldefine /* comment */ // comment
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/* comment */`resetall/*
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comment */
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/* comment */`celldefine/*
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comment */
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module cell2;
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endmodule
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/* comment */`endcelldefine/*
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comment */
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module test;
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initial $display("PASSED");
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endmodule
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