46 lines
949 B
Verilog
46 lines
949 B
Verilog
module top;
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reg pass;
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highz dutz();
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pulllow dut0();
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pullhigh dut1();
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initial begin
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pass = 1'b1;
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#10;
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if (pass) $display("PASSED");
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end
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endmodule
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module highz(in);
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input in;
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initial #1 if (in !== 1'bz) begin
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$display("FAILED: high-Z of floating input port (%b)", in);
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top.pass = 1'b0;
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end
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endmodule
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/* comment */ `unconnected_drive /* comment */ pull0 /* comment */ // comment
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module pulllow(in);
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input in;
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initial #1 if (in !== 1'b0) begin
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$display("FAILED: pull0 of floating input port (%b)", in);
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top.pass = 1'b0;
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end
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endmodule
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/* comment */ `nounconnected_drive /* comment */ // comment
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/* comment */`unconnected_drive/*
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comment */
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/* comment */pull1/*
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comment */
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module pullhigh(in);
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input in;
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initial #1 if (in !== 1'b1) begin
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$display("FAILED: pull1 of floating input port (%b)", in);
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top.pass = 1'b0;
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end
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endmodule
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/* comment */`nounconnected_drive/*
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comment */
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