52 lines
1.1 KiB
Verilog
52 lines
1.1 KiB
Verilog
/* comment */ `timescale /* comment */ // comment
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/* comment */ 1 /* comment */ // comment
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/* comment */ s /* comment */ // comment
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/* comment */ / /* comment */ // comment
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/* comment */ 100 /* comment */ // comment
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/* comment */ ms /* comment */ // comment
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module t1;
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initial begin
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$display("File %s line %0d", `__FILE__, `__LINE__);
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$printtimescale;
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end
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endmodule
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`timescale 100 ms / 10 ms // single line comment
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module t2;
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initial begin
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$display("File %s line %0d", `__FILE__, `__LINE__);
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$printtimescale;
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end
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endmodule
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`timescale 10us/1us /* another single line comment */
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module t3;
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initial begin
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$display("File %s line %0d", `__FILE__, `__LINE__);
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$printtimescale;
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end
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endmodule
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`timescale 1ns/1ps /* multi-line
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comment */
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module t4;
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initial begin
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$display("File %s line %0d", `__FILE__, `__LINE__);
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$printtimescale;
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end
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endmodule
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`timescale 1ps/1fs /* single */ /* and
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multi-line comment */
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module t5;
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initial begin
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$display("File %s line %0d", `__FILE__, `__LINE__);
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$printtimescale;
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end
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endmodule
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