22 lines
314 B
Verilog
22 lines
314 B
Verilog
module tb();
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reg [15:0] array[1:0];
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reg [3:0] shift_distance;
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wire [15:0] shifted_value;
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assign shifted_value = array[0] >> shift_distance;
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initial begin
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array[0] = 16'h1234;
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shift_distance = 4;
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#0;
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if (shifted_value === 16'h0123)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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