31 lines
409 B
Verilog
31 lines
409 B
Verilog
module test;
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event i1, i2, i3;
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integer countA, countB;
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always @(i1 or i2) begin
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$display("%0t: A", $time);
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countA = countA + 1;
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end
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always @(i2 or i3) begin
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$display("%0t: B", $time);
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countB = countB + 1;
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end
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initial begin
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countA = 0;
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countB = 0;
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#1 ->i1;
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#1 ->i2;
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#1 ->i3;
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#1;
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if (countA === 2 && countB === 2)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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