48 lines
928 B
Verilog
48 lines
928 B
Verilog
module top;
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wire [3:0][3:0] array1;
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wire [3:0][3:0] array2;
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wire [3:0][3:0] array3;
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wire [3:0][3:0] array4;
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wire [3:0][3:0] array5;
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wire [3:0][3:0] array6;
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assign array1[0+:2] = 8'h21;
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assign array1[2+:2] = 8'h43;
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assign array2[1+:2] = 8'h32;
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assign array3[1-:2] = 8'h21;
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assign array3[3-:2] = 8'h43;
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assign array4[2-:2] = 8'h32;
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assign array5[1:0] = 8'h21;
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assign array5[3:2] = 8'h43;
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assign array6[2:1] = 8'h32;
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reg failed = 0;
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initial begin
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$display("%h", array1);
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if (array1 !== 16'h4321) failed = 1;
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$display("%h", array2);
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if (array2 !== 16'hz32z) failed = 1;
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$display("%h", array3);
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if (array3 !== 16'h4321) failed = 1;
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$display("%h", array4);
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if (array4 !== 16'hz32z) failed = 1;
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$display("%h", array5);
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if (array5 !== 16'h4321) failed = 1;
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$display("%h", array6);
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if (array6 !== 16'hz32z) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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