27 lines
393 B
Verilog
27 lines
393 B
Verilog
package ivl_uvm_pkg;
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virtual class uvm_test;
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task ok;
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$display("PASSED");
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endtask
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endclass : uvm_test
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endpackage : ivl_uvm_pkg
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package test_pkg;
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import ivl_uvm_pkg::*;
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class sanity_test extends uvm_test;
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endclass : sanity_test
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endpackage : test_pkg
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module m;
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import test_pkg::*;
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sanity_test obj;
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initial begin
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obj = new;
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obj.ok;
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end
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endmodule : m
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