40 lines
713 B
Verilog
40 lines
713 B
Verilog
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module tb;
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string txt_i, txt_r, txt_h;
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int val_i;
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int val_h;
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real val_r;
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initial begin
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txt_i = "123";
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txt_r = "1.25";
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txt_h = "dead";
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val_i = txt_i.atoi();
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val_r = txt_r.atoreal();
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val_h = txt_h.atohex();
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$display("txt_i=%s, val_i=%0d", txt_i, val_i);
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if (val_i !== 123) begin
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$display("FAILED");
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$finish;
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end
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$display("txt_r=%s, val_r=%0f", txt_r, val_r);
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if (val_r != 1.25) begin
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$display("FAILED");
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$finish;
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end
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$display("txt_h=%s, val_h=%0h", txt_h, val_h);
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if (val_h !== 'hdead) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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