41 lines
711 B
Verilog
41 lines
711 B
Verilog
package test_pkg;
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class uvm_phase;
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function void print(string str);
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$display(str);
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endfunction
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endclass : uvm_phase
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class uvm_component;
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virtual function void build_phase(uvm_phase phase);
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phase.print("building");
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endfunction : build_phase
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virtual task run_phase(uvm_phase phase);
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phase.print("running");
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endtask : run_phase
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virtual task run_all();
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uvm_phase p0;
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p0 = new();
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this.build_phase(p0);
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this.run_phase(p0);
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endtask : run_all
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endclass : uvm_component
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endpackage : test_pkg
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module m;
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import test_pkg::*;
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uvm_component u0;
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initial begin : test
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u0 = new();
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u0.run_all();
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end : test
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endmodule : m
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