17 lines
297 B
Verilog
17 lines
297 B
Verilog
// Regression test for GitHub issue 13 : Icarus Verilog creates huge in-memory
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// arrays for shifts with large rhs.
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module bug();
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localparam [4:0] p = 1'b1 << ~40'b0;
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initial begin
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$display("%b", p);
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if (p === 5'b00000)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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