27 lines
343 B
Verilog
27 lines
343 B
Verilog
// Regression test for GitHub issue 12 : Ternary lval-rval width mismatch.
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module bug();
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wire [1:0] a;
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wire [1:0] y;
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assign a = 2'b10;
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assign y = 'bx ? 2'b00 : a;
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reg failed = 0;
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initial begin
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#0;
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$display("%b", y);
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if (y !== 2'bx0) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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