31 lines
396 B
Verilog
31 lines
396 B
Verilog
class testclass;
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task start();
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top.dut.signal = 1;
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endtask
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endclass
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module dut();
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logic signal = 0;
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initial begin
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$display(signal);
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@(signal);
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$display(signal);
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if (signal === 1)
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$display("PASSED");
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else
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$display("FAILED");
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$finish;
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end
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endmodule
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module top();
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testclass tc;
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initial begin
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#1 tc.start();
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end
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dut dut();
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endmodule
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