42 lines
537 B
Verilog
42 lines
537 B
Verilog
module test();
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reg clk;
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reg sel;
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reg [7:0] a;
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reg [6:0] b;
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reg [5:0] q;
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(* ivl_synthesis_on *)
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always @(posedge clk) begin
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if (sel)
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q <= b;
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else
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q <= a;
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end
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(* ivl_synthesis_off *)
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reg failed;
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initial begin
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a = 'haa;
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b = 'hbb;
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clk = 0;
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sel = 0;
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#1 clk = 1;
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#1 clk = 0;
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$display("%h", q);
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if (q !== 6'h2a) failed = 1;
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sel = 1;
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#1 clk = 1;
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#1 clk = 0;
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$display("%h", q);
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if (q !== 6'h3b) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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