55 lines
711 B
Verilog
55 lines
711 B
Verilog
module br993a();
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reg clk;
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reg a;
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reg b;
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reg [1:0] q;
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(* ivl_synthesis_on *)
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always @(posedge clk) begin
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q <= 0;
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if (a) q <= 1;
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if (b) q <= 2;
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end
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(* ivl_synthesis_off *)
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reg failed;
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initial begin
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clk = 0;
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a = 0;
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b = 0;
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#1 clk = 1;
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#1 clk = 0;
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$display("%d", q);
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if (q !== 2'd0) failed = 1;
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a = 1;
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b = 0;
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#1 clk = 1;
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#1 clk = 0;
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$display("%d", q);
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if (q !== 2'd1) failed = 1;
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a = 1;
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b = 1;
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#1 clk = 1;
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#1 clk = 0;
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$display("%d", q);
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if (q !== 2'd2) failed = 1;
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a = 0;
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b = 1;
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#1 clk = 1;
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#1 clk = 0;
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$display("%d", q);
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if (q !== 2'd2) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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