29 lines
429 B
Verilog
29 lines
429 B
Verilog
`define my_macro(a,b) localparam `` i``a``b``j = 8'h``a``b; \
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\
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module test();
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`my_macro(0,1)
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`my_macro( 2, 3)
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`my_macro( 4 , 5 )
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reg failed = 0;
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initial begin
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$display("%h", i01j);
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if (i01j !== 8'h01) failed = 1;
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$display("%h", i23j);
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if (i23j !== 8'h23) failed = 1;
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$display("%h", i45j);
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if (i45j !== 8'h45) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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