21 lines
328 B
Verilog
21 lines
328 B
Verilog
// Regression test for bug #973
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module test();
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typedef enum bit { A0, A1 } A;
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typedef enum logic { B0, B1 } B;
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typedef enum reg { C0, C1 } C;
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A enum1;
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B enum2;
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C enum3;
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initial begin
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if ($bits(enum1) == 1 && $bits(enum2) == 1 && $bits(enum3) == 1)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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