30 lines
415 B
Verilog
30 lines
415 B
Verilog
module test();
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reg in;
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wire out;
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assign out = out | in;
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reg failed;
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initial begin
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#1 in = 0;
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#0 $display("out = %b", out);
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if (out !== 1'bx) failed = 1;
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#1 in = 1;
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#0 $display("out = %b", out);
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if (out !== 1'b1) failed = 1;
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#1 in = 0;
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#0 $display("out = %b", out);
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if (out !== 1'b1) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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$finish;
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end
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endmodule
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