41 lines
880 B
Verilog
41 lines
880 B
Verilog
// Regression test for br962 - based on test case provided in bug report
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module qtest;
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parameter width = 32;
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parameter depth = 32;
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reg [width-1:0] values[$];
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reg [$clog2(depth)+width-1:0] sum1;
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reg [$clog2(depth)+width-1:0] sum2;
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task new_sample;
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input [width-1:0] data;
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int i;
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begin
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reg [width-1:0] popped;
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if (values.size >= depth)
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begin : foo
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popped = values.pop_back();
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sum1 = sum1 - popped;
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end
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sum1 = sum1 + data;
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values.push_front(data);
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sum2 = 0;
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for (i = 0; i < values.size; i++) begin
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sum2 = sum2 + values[i];
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end
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$display("sum1 = %d sum2 = %d", sum1, sum2);
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if (sum1 !== sum2) begin
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$display("FAILED");
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$finish;
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end
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end
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endtask
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initial begin
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sum1 = 0;
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repeat (2*depth) new_sample({$random});
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$display("PASSED");
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end
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endmodule
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