49 lines
888 B
Verilog
49 lines
888 B
Verilog
package test_pkg;
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// Need to add enumerations to packages.
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typedef enum logic[4:0] {
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EXC_A = 0,
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EXC_B = 1,
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EXC_C = 2
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} exc_code_t;
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// Need to search up the parent scope searching for the enum definition.
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function logic func1(exc_code_t c);
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logic rVal;
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case(c)
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EXC_C : rVal = 1;
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default: rVal = 0;
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endcase
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return(rVal);
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endfunction
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endpackage
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module a();
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import test_pkg::func1;
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import test_pkg::exc_code_t;
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exc_code_t exc_code;
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logic result;
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initial begin
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// Need to compare the base enumeration definition to check compatibility.
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exc_code = test_pkg::EXC_C;
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result = func1(exc_code);
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if(result==1'b1) begin
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$display("PASSED");
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$finish;
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end
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$display("FAILED");
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$finish;
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end
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endmodule
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