108 lines
2.2 KiB
Verilog
108 lines
2.2 KiB
Verilog
`timescale 1 ps / 1 ps
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module mux_2_to_1
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(
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input sel_i,
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input [1:0] dat_i,
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output dat_o
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);
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assign dat_o = sel_i && dat_i[1] || ~sel_i && dat_i[0];
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endmodule
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module mux_n_to_1
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#(
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parameter sel_w = 4,
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parameter n_inputs = 2**sel_w
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)
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(
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input [n_inputs-1:0] inputs_i,
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input [sel_w-1:0] sel_i,
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output output_o
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);
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genvar i,j;
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generate
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if(sel_w == 1) begin
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mux_2_to_1 mux_simple
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(
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.sel_i(sel_i),
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.dat_i(inputs_i),
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.dat_o(output_o)
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);
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end else begin
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wire [n_inputs-2:0] inter_w;
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for(i=0; i<sel_w; i=i+1) begin : SELECT_STAGE
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if(i==0) begin
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for(j=0; j<n_inputs/2; j=j+1) begin : FIRST_STAGE
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mux_2_to_1 mux_first_stage
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(
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.sel_i(sel_i[i]),
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.dat_i(inputs_i[2*j+1:2*j]),
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.dat_o(inter_w[j])
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);
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end
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end else begin
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for(j=0; j<(n_inputs/(2**(i+1))); j=j+1) begin : INTERMEDIARY_STAGE
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mux_2_to_1 mux_intermediary_stages
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(
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.sel_i(sel_i[i]),
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.dat_i(inter_w[ (n_inputs/(2**(i-1)))*((2**(i-1))-1) + 2*j + 1 : (n_inputs/(2**(i-1)))*((2**(i-1))-1) + 2*j ]),
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.dat_o(inter_w[ (n_inputs/(2**i))*((2**i)-1) + j ])
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);
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end
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end
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end
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assign output_o = inter_w[ (n_inputs/(2**(sel_w-1)))*((2**(sel_w-1))-1) ];
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end
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endgenerate
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endmodule
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module top;
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parameter sel_wid = 3;
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parameter num_inputs = 2**sel_wid;
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reg [num_inputs-1:0] in;
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reg [sel_wid-1:0] sel;
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wire out;
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integer lp;
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reg pass;
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mux_n_to_1
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#(
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.sel_w(sel_wid),
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.n_inputs(num_inputs)
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)
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dut
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(
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.inputs_i(in),
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.sel_i(sel),
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.output_o(out)
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);
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initial begin
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pass = 1'b1;
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for (lp = 0; lp < num_inputs; lp = lp + 1) begin
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sel = lp;
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in = 2**lp;
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$display("Checking input %0d;", sel);
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#1;
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if (out !== 1'b1) begin
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$display(" Failed input high (%b), got %b", in, out);
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pass = 1'b0;
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end
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in = ~in;
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#1;
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if (out !== 1'b0) begin
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$display(" Failed input low (%b), got %b", in, out);
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pass = 1'b0;
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end
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end
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if (pass) $display("PASSED");
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end
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endmodule
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