71 lines
2.0 KiB
Verilog
71 lines
2.0 KiB
Verilog
module top;
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reg pass;
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reg in;
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reg pout;
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wire out;
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function invert;
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input in;
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// When this is a named block the compiler creates a fork/join to
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// create the new scope. The problem with this is that of_EXEC_UFUNC
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// opcode does not work correctly since the vthread_run(child) call
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// returns when the join is executed which then copies the return value
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// before the function body code has actually run. This causes the
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// results to be delayed by one call. Does this need to be split into
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// two functions. One that acts like fork and copies the input values
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// and one that acts like join and returns the function result?
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// It appears that procedural user function calls work correctly since
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// they use fork/join to call the user function.
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// Both V0.9 and development have this problem.
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begin: block_name
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invert = ~in;
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$display("Function should return %b when given %b.", invert, in);
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end
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endfunction
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assign out = invert(in);
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initial begin
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pass = 1'b1;
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in = 1'b0;
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#1;
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if (out !== 1'b1) begin
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$display("CA result was %b when given %b, expect 1'b1.", out, in);
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pass = 1'b0;
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end
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pout = invert(in);
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if (pout !== 1'b1) begin
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$display("Result was %b when given %b, expect 1'b1.", pout, in);
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pass = 1'b0;
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end
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in = 1'b1;
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#1;
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if (out !== 1'b0) begin
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$display("CA result was %b when given %b, expect 1'b0.", out, in);
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pass = 1'b0;
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end
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pout = invert(in);
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if (pout !== 1'b0) begin
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$display("Result was %b when given %b, expect 1'b0.", pout, in);
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pass = 1'b0;
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end
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in = 1'bz;
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#1;
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if (out !== 1'bx) begin
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$display("CA result was %b when given %b, expect 1'bx.", out, in);
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pass = 1'b0;
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end
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pout = invert(in);
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if (pout !== 1'bx) begin
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$display("Result was %b when given %b, expect 1'bx.", pout, in);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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