38 lines
658 B
Verilog
38 lines
658 B
Verilog
// Regression test for SF bug 947 : Procedural continuous assignment
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// affects other structural connections to source vector.
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`timescale 1ns/1ps
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module test();
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wire delay0;
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wire delay1;
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wire delay2;
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reg select;
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reg out;
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assign #100 delay0 = 1;
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assign #100 delay1 = delay0;
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assign #100 delay2 = delay1;
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always @(select) begin
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if (select)
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assign out = delay2;
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else
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assign out = delay0;
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end
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initial begin
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$monitor($time,, delay0,, delay1,, delay2,, out);
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select = 0;
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#250;
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select = 1;
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#300;
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if ((delay0 == 1) && (delay1 == 1) && (delay2 == 1) && (out == 1))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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