36 lines
857 B
Verilog
36 lines
857 B
Verilog
module top;
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reg test;
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event ev;
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reg val;
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initial begin
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#10;
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test = 1'b1;
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#20;
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$display("FAILED");
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// I would expect this watchdog to require a $finish() since the other
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// initial did not finish, but it's not needed so that implies the
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// other initial is getting disabled not just the named begin.
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end
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initial begin
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test = 1'b0;
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val = 1'b0;
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fork
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// With the @ line here development fails. If it is after the named
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// begin it passes.
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@(test) disable nb;
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begin : nb
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// Any blocking item here causes the problem.
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// wait(val);
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// @(ev);
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#20;
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end
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join
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// This is never executed even though it should run at time 10.
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$display("PASSED");
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// The finish is required to prevent the watchdog from running.
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$finish;
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end
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endmodule
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