44 lines
502 B
Verilog
44 lines
502 B
Verilog
module bug();
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reg flag1;
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reg flag2;
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task task1(inout integer flag);
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begin
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#4 flag = 1;
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end
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endtask
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task task2(inout integer flag);
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begin
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#5 flag = 1;
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end
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endtask
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task task3(inout flag1, inout flag2);
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fork
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task1(flag1);
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task2(flag2);
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join
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endtask
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initial begin
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flag1 = 0;
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flag2 = 0;
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task3(flag1, flag2);
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$display("flag1 = %d", flag1);
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$display("flag2 = %d", flag2);
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if ((flag1 === 1) && (flag2 === 1))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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