36 lines
858 B
Verilog
36 lines
858 B
Verilog
module top;
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reg pass;
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reg we;
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reg [7:0] c;
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reg signed [7:0] res;
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initial begin
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pass = 1'b1;
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c = 8'd3;
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we = 1'b1;
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// $display ("res(we) = %d", (we ? (-$signed(c)) / 8'sd2 : 8'd1));
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// $display ("res(1) = %d", (1'b1 ? (-$signed(c)) / 8'sd2 : 8'd1));
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res = we ? (-$signed(c)) / 8'sd2 : 8'd1;
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if (res !== 126) begin
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$display("Failed: variable ternary, expected 126, got %d", res);
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pass = 1'b0;
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end
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res = 1'b1 ? (-$signed(c)) / 8'sd2 : 8'd1;
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if (res !== 126) begin
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$display("Failed: constant true ternary, expected 126, got %d", res);
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pass = 1'b0;
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end
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res = 1'b0 ? 8'd1 : (-$signed(c)) / 8'sd2;
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if (res !== 126) begin
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$display("Failed: constant false ternary, expected 126, got %d", res);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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