58 lines
1.6 KiB
Verilog
58 lines
1.6 KiB
Verilog
module br918d;
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reg pass;
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reg [1:0] v1, v2, v3, v4;
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wire [3:0] w1, w2, w3, w4;
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// Assign as pieces with matching strengths.
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assign (pull1,strong0) w1[1:0] = v1;
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assign (pull1,strong0) w1[1:0] = v2;
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assign (pull1,strong0) w1[3:2] = v3;
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assign (pull1,strong0) w1[3:2] = v4;
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// Assign with a concat.
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assign (pull1,strong0) w2 = {v3, v1};
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assign (pull1,strong0) w2 = {v4, v2};
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// Only assign part
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assign (pull1,strong0) w3[1:0] = v1;
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assign (pull1,strong0) w3[1:0] = v2;
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// Assign as pieces with different strengths.
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assign (pull1,strong0) w4[1:0] = v1;
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assign (pull1,strong0) w4[1:0] = v2;
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assign (strong1,pull0) w4[3:2] = v3;
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assign (strong1,pull0) w4[3:2] = v4;
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initial begin
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pass = 1'b1;
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v1 = 2'b00;
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v2 = 2'b10;
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v3 = 2'b11;
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v4 = 2'b10;
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#1;
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// Check the assign as pieces (this is the same as br918a)
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if (w1 !== 4'b1000) begin
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$display("FAILED: assign with pieces (1), expected 4'b1000, got %b", w1);
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pass = 1'b0;
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end
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// Check the assign with a concat.
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if (w2 !== 4'b1000) begin
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$display("FAILED: assign with concat, expected 4'b1000, got %b", w2);
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pass = 1'b0;
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end
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// Check when only a piece is assigned (other compilers may return xx00).
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if ((w3 !== 4'bzz00) && (w3 !== 4'bxx00)) begin
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$display("FAILED: assign part, expected 4'bzz00 or 4'bxx00, got %b", w3);
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pass = 1'b0;
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end
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// Check the assign as pieces (this is the same as br918a)
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if (w4 !== 4'b1100) begin
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$display("FAILED: assign with pieces (2), expected 4'b1000, got %b", w4);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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