34 lines
1.2 KiB
Verilog
34 lines
1.2 KiB
Verilog
module top;
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function real copy(input real r);
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copy = r;
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endfunction
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real a, b, c, d, e, f;
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initial begin
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a = 0.4;
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b = 0.5;
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c = 0.6;
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d = 2.4;
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e = 2.5;
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f = 2.6;
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$display("a: %.1f %0d %0x %0b", copy(a), copy(a), copy(a), copy(a));
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$display("b: %.1f %0d %0x %0b", copy(b), copy(b), copy(b), copy(b));
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$display("c: %.1f %0d %0x %0b", copy(c), copy(c), copy(c), copy(c));
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$display("d: %.1f %0d %0x %0b", copy(d), copy(d), copy(d), copy(d));
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$display("e: %.1f %0d %0x %0b", copy(e), copy(e), copy(e), copy(e));
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$display("f: %.1f %0d %0x %0b", copy(f), copy(f), copy(f), copy(f));
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a = -0.4;
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b = -0.5;
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c = -0.6;
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d = -2.4;
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e = -2.5;
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f = -2.6;
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$display("a: %.1f %0d %0x %0b", copy(a), copy(a), copy(a), copy(a));
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$display("b: %.1f %0d %0x %0b", copy(b), copy(b), copy(b), copy(b));
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$display("c: %.1f %0d %0x %0b", copy(c), copy(c), copy(c), copy(c));
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$display("d: %.1f %0d %0x %0b", copy(d), copy(d), copy(d), copy(d));
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$display("e: %.1f %0d %0x %0b", copy(e), copy(e), copy(e), copy(e));
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$display("f: %.1f %0d %0x %0b", copy(f), copy(f), copy(f), copy(f));
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end
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endmodule
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