40 lines
480 B
Verilog
40 lines
480 B
Verilog
module dut(
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input wire [3:0] i,
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output wire [3:0] o
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);
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assign o = i;
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specify
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(i[3:0] => o[3:0]) = (1, 1);
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endspecify
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endmodule
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module top();
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reg [3:0] i;
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wire [3:0] o;
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dut dut(i, o);
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reg failed = 0;
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initial begin
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$monitor($time,,i,,o);
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#1 i = 4'd1;
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#0 if (o !== 4'bx) failed = 1;
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#1 i = 4'd2;
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#0 if (o !== 4'd1) failed = 1;
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#1;
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#0 if (o !== 4'd2) failed = 1;
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#1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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