68 lines
1.6 KiB
Verilog
68 lines
1.6 KiB
Verilog
//
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// Copyright (c) 1999 Stephan Boettcher (stephan@nevis1.nevis.columbia.edu)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - PR 204 report - validates correct use of blank ports.
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module none;
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reg x;
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endmodule // none
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module empty();
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reg x;
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endmodule // none
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module one (a);
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input a;
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reg x;
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endmodule // one
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module two (a, b);
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input a, b;
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reg x;
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endmodule // two
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module three (a, b, c);
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input a, b, c;
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reg x;
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endmodule // two
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module main;
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wire w1, w2, w3, w4, w5, w6, w7, w8, w9;
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none U1 ();
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empty U2 ();
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one U3 ();
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one U4 (w1);
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one U5 (.a(w2));
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two U6 ();
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two U7 (,);
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two U8 (w3,);
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two U9 (,w4);
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two Ua (w5,w6);
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two Ub (.a(w7));
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two Uc (.b(w8));
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two Ud (.b(w8),.a(w9));
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three Ue ();
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//three Uf (,); //XXXX I doubt this is legal... ?
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three Ug (,,);
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initial $display("PASSED");
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endmodule // main
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