35 lines
673 B
Verilog
35 lines
673 B
Verilog
// Check that passing a data type to $bits works as expected
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module test;
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bit failed = 1'b0;
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`define check(type, value) \
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if ($bits(type) !== value) begin \
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$display("FAILED: $bits(", `"type`", ") is %0d", $bits(type), " expected %0d", value); \
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failed = 1'b1; \
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end
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typedef int T1;
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typedef int T2[3:0];
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initial begin
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`check(reg, 1);
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`check(logic, 1);
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`check(bit, 1);
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`check(logic [3:0], 4);
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`check(byte, 8);
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`check(shortint, 16);
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`check(int, 32);
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`check(longint, 64);
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`check(struct packed { int x; shortint y; }, 32 + 16);
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`check(T1, 32);
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`check(T2, 4 * 32);
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if (failed == 1'b0) begin
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$display("PASSED");
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end
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end
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endmodule
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