27 lines
441 B
Verilog
27 lines
441 B
Verilog
module automatic_task();
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reg [7:0] array[3:0];
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task automatic fill_array;
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input [7:0] value;
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integer i, j;
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fork
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for (i = 0; i < 4; i = i + 1) begin
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#10 array[i] = value;
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end
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for (j = 0; j < 4; j = j + 1) begin
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@(array[j]) $display(array[0], array[1], array[2], array[3]);
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@(array[j]) $display(array[0], array[1], array[2], array[3]);
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end
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join
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endtask
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initial #1 fill_array(1);
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initial #2 fill_array(2);
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endmodule
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