83 lines
2.5 KiB
Verilog
83 lines
2.5 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate always casex ( reg_value) case_item1; case_item2; case_item3; endcase
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// D:
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module main ;
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reg [3:0] value1,value2,value3;
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initial
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begin
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#0;
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value3 = 0;
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#1 ; // t=3
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value1 = 4'b0000 ; // Picked up at time 6
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#9 ; // check at time 10
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if(value2 != 4'b0)
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begin
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$display("FAILED - always3.1.6B - casex 0 at %t",$time);
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value3 = 1;
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end
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#1 ; // Picked up at time 12
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value1 = 4'b0011 ; // Set at time 11.
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#5 ; // Check at time 16
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if(value2 != 4'b0001)
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begin
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$display("FAILED - always3.1.6B - casex 1 at %t",$time);
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value3 = 1;
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end
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#1; // Picked up at time 16
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value1 = 4'b0100; // Changed at time 15.
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#5; // Check at time 20...
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if(value2 != 4'b0010)
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begin
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$display("FAILED - always3.1.6B - casex 2 at %t",$time);
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value3 = 1;
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end
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#10;
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if(value3 == 0)
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$display("PASSED");
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$finish;
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end
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always casex (value1)
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4'b0000: begin
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#3 ;
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value2 = 4'b0000 ;
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#3 ;
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end
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4'b00x1: begin
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#3 ;
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value2 = 4'b0001 ;
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#3 ;
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end
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4'b0100: begin
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#3 ;
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value2 = 4'b0010 ;
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#3 ;
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end
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endcase
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endmodule
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