26 lines
573 B
Verilog
26 lines
573 B
Verilog
module main;
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reg [8:0] val;
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ornor8 dut (.O_OR(o_or), .O_NOR(o_nor),
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.I0(val[0]), .I1(val[1]), .I2(val[2]), .I3(val[3]),
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.I4(val[4]), .I5(val[5]), .I6(val[6]), .I7(val[7]));
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initial begin
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for (val = 0 ; val[8] == 0 ; val = val+1) begin
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#1 if (o_or !== |val[7:0]) begin
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$display("FAILED -- |%b --> %b", val[7:0], o_or);
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$finish;
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end
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if (o_nor !== ~|val[7:0]) begin
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$display("FAILED -- ~|%b --> %b", val[7:0], o_nor);
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$finish;
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end
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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