14 lines
398 B
Verilog
14 lines
398 B
Verilog
module eqne(output wire eq1, output wire ne1,
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output wire eq2, output wire ne2,
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output wire eq5, output wire ne5,
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input wire [7:0] x, input wire [7:0] y);
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assign eq1 = x[0] == y[0];
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assign ne1 = x[0] != y[0];
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assign eq2 = x[1:0] == y[1:0];
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assign ne2 = x[1:0] != y[1:0];
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assign eq5 = x[4:0] == y[4:0];
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assign ne5 = x[4:0] != y[4:0];
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endmodule // eqne
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