80 lines
2.4 KiB
Verilog
80 lines
2.4 KiB
Verilog
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/*
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* This is a post-synthesis test for the blif_shift.v test. Run this
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* simulation in these steps:
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*
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* $ iverilog -tblif -o foo.blif blif_shift.v
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* $ abc
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* abc 01> read_blif foo.blif
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* abc 02> write_verilog foo.v
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* abc 03> quit
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* $ iverilog -g2009 -o foo.vvp blif_shift_tb.v foo.v
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* $ vvp foo.vvp
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*/
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module main;
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parameter W=3;
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reg [W:0] D;
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reg [W:0] S;
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parameter WO=5;
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wire [WO:0] SHL;
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wire [WO:0] SHR;
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wire [WO:0] ASHL;
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wire [WO:0] ASHR;
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reg [WO:0] shl;
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reg [WO:0] shr;
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reg [WO:0] ashl;
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reg [WO:0] ashr;
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`ifdef DUMMY
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shift ss(.D (D), .S (S), .SHL (SHL), .SHR (SHR), .ASHL (ASHL), .ASHR (ASHR));
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`else
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shift ss(.\D[3] (D[3]), .\D[2] (D[2]), .\D[1] (D[1]), .\D[0] (D[0]),
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.\S[3] (S[3]), .\S[2] (S[2]), .\S[1] (S[1]), .\S[0] (S[0]),
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.\SHL[5] (SHL[5]), .\SHL[4] (SHL[4]), .\SHL[3] (SHL[3]), .\SHL[2] (SHL[2]), .\SHL[1] (SHL[1]), .\SHL[0] (SHL[0]),
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.\SHR[5] (SHR[5]), .\SHR[4] (SHR[4]), .\SHR[3] (SHR[3]), .\SHR[2] (SHR[2]), .\SHR[1] (SHR[1]), .\SHR[0] (SHR[0]),
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.\ASHL[5] (ASHL[5]), .\ASHL[4] (ASHL[4]), .\ASHL[3] (ASHL[3]), .\ASHL[2] (ASHL[2]), .\ASHL[1] (ASHL[1]), .\ASHL[0] (ASHL[0]),
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.\ASHR[5] (ASHR[5]), .\ASHR[4] (ASHR[4]), .\ASHR[3] (ASHR[3]), .\ASHR[2] (ASHR[2]), .\ASHR[1] (ASHR[1]), .\ASHR[0] (ASHR[0]));
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`endif
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int ddx;
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int sdx;
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initial begin
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for (ddx = 0 ; ddx < 1 << (W+1) ; ddx = ddx+1)
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for (sdx = 0 ; sdx < WO + 2 ; sdx = sdx+1) begin
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D = ddx[W:0];
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S = sdx[W:0];
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shl = D << S;
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shr = D >> S;
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ashl = $signed(D) <<< S;
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ashr = $signed(D) >>> S;
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// $display("D = %b, S = %b", D, S);
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// $display("shl = %b, shr = %b", shl, shr);
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// $display("ashl = %b, ashr = %b", ashl, ashr);
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#1;
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if (SHL !== shl) begin
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$display("FAILED -- D=%b, S=%b, SHL=%b (should be %b)", D, S, SHL, shl);
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$finish;
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end
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if (SHR !== shr) begin
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$display("FAILED -- D=%b, S=%b, SHR=%b (should be %b)", D, S, SHR, shr);
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$finish;
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end
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if (ASHL !== ashl) begin
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$display("FAILED -- D=%b, S=%b, ASHL=%b (should be %b)", D, S, ASHL, ashl);
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$finish;
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end
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if (ASHR !== ashr) begin
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$display("FAILED -- D=%b, S=%b, SHL=%b (should be %b)", D, S, ASHR, ashr);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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