121 lines
3.0 KiB
Plaintext
121 lines
3.0 KiB
Plaintext
####################
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#
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# Main test script
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#
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####################
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There are a group of tests that are meant to exercise the compiler
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and the run time. To run them just type:
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./regress
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or
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perl vvp_reg.pl
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or if perl is located in /usr/bin
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./vvp_reg.pl
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The output from these tests are displayed on the screen
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and are also placed in the regression_report.txt file.
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The expected output for the current development release
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is located in the regression_report-devel.txt file. The
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expected output for stable (released) versions can be
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found in files named regression_report-v<version>.txt.
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The results from individual tests can be found in the
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log directory and gold files, when needed, are in the
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gold directory. The source files can be found in the
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ivltests and contrib directories. The list of tests
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and how they are run are in the regress-*.list files.
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To check a specific suffixed version of Icarus Verilog
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use the --suffix=<suffix> flag to tell the script which
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version to run e.g.(--suffix=-10 will test iverilog-10,
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etc.). You can also run the test with valgrind (very very
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slow) by giving the script the --with-valgrind flag.
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####################
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#
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# VPI test script
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#
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####################
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To test the VPI interface type:
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perl vpi_reg.pl
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or if perl is located in /usr/bin
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./vpi_reg.pl
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All these tests should pass for V11.devel. There are
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some expected failures for V10, which are flagged as
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Not Implemented
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The individual test results are found in the vpi_log
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directory and the gold files are in the vpi_gold
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directory. The source files are in the vpi directory.
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The vpi_regress.list file has the tests to perform.
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This script also takes the --suffix=<suffix> and the
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--with-valgrind flags described above.
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####################
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#
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# VHDL test script
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#
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####################
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** Note this is no longer maintained **
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This test script require that ghdl be installed in your
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path and is used to test the Verilog to VHDL translation.
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perl vhdl_reg.pl
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or if perl is located in /usr/bin
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./vhdl_reg.pl
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The expected output for V0.10.devel and V0.9 is located
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in the vhdl_regression_report-devel.txt file. V0.8 does
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not support converting Verilog to VHDL.
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This script also takes the --suffix=<suffix> and the
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--with-valgrind flags described above.
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####################
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#
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# BLIF test script
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#
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####################
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This test script require that abc be installed in your
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path and is used to test the Verilog to VHDL translation.
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python blif_reg.py
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There is no expected output as of yet so to check for
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regressions simply run with and without your patches.
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####################
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#
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# Windows (MinGW) test issues
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#
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####################
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When running under Windows using a MinGW build in a MSYS2
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shell, the expected output from vvp_reg.pl can be found in
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regression_report-msys2.txt. The MinGW/MSYS2 specific test
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exceptions can be found in regress-msys2.list. Exceptions
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for the VPI tests can be found in the vpi_regress.list file.
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With Windows 10 and MSYS2, there are now very few differences
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between the Windows and Linux builds.
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