88 lines
2.6 KiB
C
88 lines
2.6 KiB
C
/*
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* Copyright (c) 2001-2010 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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# include "device.h"
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# include "fpga_priv.h"
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# include "edif.h"
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# include "generic.h"
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# include "xilinx.h"
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# include <stdlib.h>
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# include <string.h>
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# include <assert.h>
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/*
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* This is a table of cell types that are accessible via the cellref
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* attribute to a gate.
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*/
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const static struct edif_xlib_celltable virtex2_celltable[] = {
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{ "BUFG", xilinx_cell_bufg },
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{ "MULT_AND", xilinx_cell_mult_and },
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{ 0, 0}
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};
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/*
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* The show_header function is called before any of the devices of the
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* netlist are scanned.
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*
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* In this function, we look at the ports of the root module to decide
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* if they are to be made into ports. Modules that have PAD attributes
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* are *not* to be used as ports, they will be connected to special
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* PAD devices instead.
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*/
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static void virtex2_show_header(ivl_design_t des)
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{
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const char*part_str = 0;
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xilinx_common_header(des);
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xlib = edif_xlibrary_create(edf, "VIRTEX2");
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edif_xlibrary_set_celltable(xlib, virtex2_celltable);
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if ( (part_str = ivl_design_flag(des, "part")) && (part_str[0] != 0) ) {
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edif_pstring(edf, "PART", part_str);
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}
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cell_0 = edif_xcell_create(xlib, "GND", 1);
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edif_cell_portconfig(cell_0, 0, "GROUND", IVL_SIP_OUTPUT);
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cell_1 = edif_xcell_create(xlib, "VCC", 1);
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edif_cell_portconfig(cell_1, 0, "VCC", IVL_SIP_OUTPUT);
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}
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const struct device_s d_virtex2_edif = {
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virtex2_show_header,
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xilinx_show_footer,
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xilinx_show_scope,
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xilinx_pad,
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virtex_logic,
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virtex_generic_dff,
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virtex_eq,
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virtex_eq,
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virtex_ge,
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0, /* show_cmp_gt */
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virtex_mux,
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virtex_add,
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virtex_add,
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xilinx_shiftl, /* show_shiftl */
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0 /* show_shiftr */
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};
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