337 lines
8.9 KiB
C++
337 lines
8.9 KiB
C++
#ifndef __vvm_gates_H
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#define __vvm_gates_H
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/*
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* Copyright (c) 1998 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: vvm_gates.h,v 1.5 1999/01/01 01:44:56 steve Exp $"
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#endif
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# include "vvm.h"
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# include <assert.h>
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/*
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* A vvm gate is constructed with an input width and an output
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* function. The input width represents all the input signals that go
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* into generating a single output value. The output value is passed
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* to the output function, which may fan the result however makes
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* sense. The output is scheduled as an event.
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*/
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class vvm_out_event : public vvm_event {
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public:
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typedef void (*action_t)(vvm_simulation*, vvm_bit_t);
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vvm_out_event(vvm_simulation*s, vvm_bit_t v, action_t o)
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: output_(o), sim_(s), val_(v) { }
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void event_function()
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{ output_(sim_, val_); }
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private:
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const action_t output_;
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vvm_simulation*const sim_;
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const vvm_bit_t val_;
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};
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template <unsigned WIDTH, unsigned long DELAY> class vvm_and {
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public:
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explicit vvm_and(vvm_out_event::action_t o)
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: output_(o) { }
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void init(unsigned idx, vvm_bit_t val)
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{ input_[idx-1] = val; }
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void start(vvm_simulation*sim)
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{ vvm_event*ev = new vvm_out_event(sim, compute_(), output_);
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if (DELAY > 0)
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sim->insert_event(DELAY, ev);
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else
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sim->active_event(ev);
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}
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void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val)
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{ if (input_[idx-1] == val)
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return;
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input_[idx-1] = val;
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vvm_event*ev = new vvm_out_event(sim, compute_(), output_);
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if (DELAY > 0)
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sim->insert_event(DELAY, ev);
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else
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sim->active_event(ev);
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}
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private:
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vvm_bit_t compute_() const
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{ vvm_bit_t outval = input_[0];
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for (unsigned i = 1 ; i < WIDTH ; i += 1)
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outval = outval & input_[i];
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return outval;
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}
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vvm_bit_t input_[WIDTH];
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vvm_out_event::action_t output_;
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};
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template <unsigned WIDTH, unsigned long DELAY> class vvm_nand {
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public:
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explicit vvm_nand(vvm_out_event::action_t o)
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: output_(o)
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{ for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
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input_[idx] = V0;
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}
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void init(unsigned idx, vvm_bit_t val) { input_[idx-1] = val; }
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// Set an input of the NAND gate causes a new output value to
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// be calculated and an event generated to make the output
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// happen. The input pins are numbered from 1 - WIDTH.
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void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val)
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{ if (input_[idx-1] == val)
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return;
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input_[idx-1] = val;
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vvm_bit_t outval = input_[0];
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for (unsigned i = 1 ; i < WIDTH ; i += 1)
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outval = outval & input_[i];
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vvm_event*ev = new vvm_out_event(sim, not(outval), output_);
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if (DELAY > 0)
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sim->insert_event(DELAY, ev);
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else
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sim->active_event(ev);
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}
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private:
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vvm_bit_t input_[WIDTH];
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vvm_out_event::action_t output_;
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};
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/*
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* Simple inverter buffer.
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*/
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template <unsigned long DELAY> class vvm_not {
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public:
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explicit vvm_not(vvm_out_event::action_t o)
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: output_(o)
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{ }
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void init(unsigned, vvm_bit_t) { }
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void start(vvm_simulation*) { }
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void set(vvm_simulation*sim, unsigned, vvm_bit_t val)
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{ vvm_bit_t outval = not(val);
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vvm_event*ev = new vvm_out_event(sim, outval, output_);
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if (DELAY > 0)
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sim->insert_event(DELAY, ev);
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else
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sim->active_event(ev);
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}
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private:
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vvm_out_event::action_t output_;
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};
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template <unsigned WIDTH, unsigned long DELAY> class vvm_xnor {
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public:
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explicit vvm_xnor(vvm_out_event::action_t o)
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: output_(o) { }
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void init(unsigned idx, vvm_bit_t val) { input_[idx-1] = val; }
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void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val)
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{ if (input_[idx-1] == val)
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return;
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input_[idx-1] = val;
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vvm_bit_t outval = input_[0];
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for (unsigned i = 1 ; i < WIDTH ; i += 1)
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outval = outval ^ input_[i];
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outval = not(outval);
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vvm_event*ev = new vvm_out_event(sim, outval, output_);
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if (DELAY > 0)
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sim->insert_event(DELAY, ev);
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else
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sim->active_event(ev);
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}
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private:
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vvm_bit_t input_[WIDTH];
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vvm_out_event::action_t output_;
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};
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template <unsigned WIDTH, unsigned long DELAY> class vvm_xor {
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public:
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explicit vvm_xor(vvm_out_event::action_t o)
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: output_(o) { }
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void init(unsigned idx, vvm_bit_t val)
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{ input_[idx-1] = val; }
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void start(vvm_simulation*sim)
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{ vvm_event*ev = new vvm_out_event(sim, compute_(), output_);
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if (DELAY > 0)
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sim->insert_event(DELAY, ev);
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else
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sim->active_event(ev);
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}
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void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val)
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{ if (input_[idx-1] == val)
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return;
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input_[idx-1] = val;
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start(sim);
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}
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private:
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vvm_bit_t compute_() const
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{ vvm_bit_t outval = input_[0];
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for (unsigned i = 1 ; i < WIDTH ; i += 1)
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outval = outval ^ input_[i];
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return outval;
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}
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vvm_bit_t input_[WIDTH];
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vvm_out_event::action_t output_;
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};
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/*
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* A Sequential UDP has a more complex truth table, and handles
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* edges. Pin 0 is an output, and all the remaining pins are
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* input. The WIDTH is the number of input pins.
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*
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* See vvm.txt for a description of the gate transition table.
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*/
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template <unsigned WIDTH> class vvm_udp_ssequ {
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public:
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explicit vvm_udp_ssequ(vvm_out_event::action_t o, vvm_bit_t i,
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const vvm_u32*tab)
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: output_(o), table_(tab)
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{ state_[0] = i;
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for (unsigned idx = 1; idx < WIDTH+1 ; idx += 1)
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state_[idx] = Vx;
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}
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void init(unsigned pin, vvm_bit_t val)
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{ state_[pin] = val; }
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void set(vvm_simulation*sim, unsigned pin, vvm_bit_t val)
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{ assert(pin > 0);
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assert(pin < WIDTH+1);
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if (val == Vz) val = Vx;
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if (state_[pin] == val) return;
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// Convert the current state into a table index.
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unsigned entry = 0;
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for (unsigned idx = 0 ; idx < WIDTH+1 ; idx += 1) {
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entry *= 3;
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entry += state_[idx];
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}
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// Get the table entry, and the 4bits that encode
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// activity on this pin.
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vvm_u32 code = table_[entry];
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code >>= 4 * (WIDTH-pin);
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switch (state_[pin]*4 + val) {
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case (V0*4 + V1):
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case (V1*4 + V0):
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case (Vx*4 + V0):
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code = (code>>2) & 3;
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break;
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case (V0*4 + Vx):
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case (V1*4 + Vx):
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case (Vx*4 + V1):
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code &= 3;
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break;
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}
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// Convert the code to a vvm_bit_t and run with it.
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vvm_bit_t outval = (code == 0)? V0 : (code == 1)? V1 : Vx;
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state_[0] = outval;
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state_[pin] = val;
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vvm_event*ev = new vvm_out_event(sim, outval, output_);
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sim->insert_event(1, ev); // XXXX Delay not supported.
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}
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private:
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vvm_out_event::action_t output_;
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const vvm_u32*const table_;
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vvm_bit_t state_[WIDTH+1];
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};
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class vvm_bufz {
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public:
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explicit vvm_bufz(vvm_out_event::action_t o)
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: output_(o)
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{ }
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void init(unsigned idx, vvm_bit_t val) { }
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void set(vvm_simulation*sim, unsigned idx, vvm_bit_t val)
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{ output_(sim, val); }
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private:
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vvm_out_event::action_t output_;
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};
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class vvm_pevent {
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public:
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enum EDGE { ANYEDGE, POSEDGE, NEGEDGE };
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explicit vvm_pevent();
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void wait(EDGE, vvm_thread*);
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void set(vvm_simulation*sim, unsigned, vvm_bit_t val);
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vvm_bit_t get() const { return value_; }
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private:
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vvm_bit_t value_;
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vvm_thread*hold_;
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EDGE hold_edge_;
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private: // not implemented
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vvm_pevent(const vvm_pevent&);
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vvm_pevent& operator= (const vvm_pevent&);
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};
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/*
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* $Log: vvm_gates.h,v $
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* Revision 1.5 1999/01/01 01:44:56 steve
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* Support the start() method.
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*
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* Revision 1.4 1998/12/20 02:05:41 steve
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* Function to calculate wire initial value.
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*
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* Revision 1.3 1998/12/17 23:54:58 steve
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* VVM support for small sequential UDP objects.
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*
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* Revision 1.2 1998/11/10 00:48:31 steve
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* Add support it vvm target for level-sensitive
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* triggers (i.e. the Verilog wait).
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* Fix display of $time is format strings.
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*
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* Revision 1.1 1998/11/09 23:44:11 steve
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* Add vvm library.
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*
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*/
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#endif
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