57 lines
1.4 KiB
Verilog
57 lines
1.4 KiB
Verilog
//
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// Copyright (c) 1999 Peter Monta (pmonta@imedia.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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module main;
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wire [3:0] a,b,c,d,e,f;
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ma a1(a);
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ma #(4'd9) a2(b);
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mb #(4'd12) b1(c);
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mb b2(d);
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mc #(4'd2) c1(e,f);
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initial begin
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#1;
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if (a===4'd5 && b===4'd9 && c===4'd12 && d===4'd7 && e===4'd2 && f===4'd3)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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module ma(x);
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output [3:0] x;
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parameter P = 4'd5;
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assign x = P;
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endmodule
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module mb(x);
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output [3:0] x;
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parameter Q = 4'd7;
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ma #(Q) a1(x);
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endmodule
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module mc(x,y);
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output [3:0] x,y;
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parameter R = 4'd1;
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parameter S = 4'd3;
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ma #(R) a1(x);
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ma #(S) a2(y);
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endmodule
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