46 lines
1012 B
Verilog
46 lines
1012 B
Verilog
module m1();
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parameter p = 0;
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endmodule
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module m2();
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generate
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genvar i;
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for (i = 0; i < 2; i = i + 1) begin : Loop1
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m1 m();
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defparam m.p = 1 + i;
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end
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for (i = 2; i < 4; i = i + 1) begin : Loop2
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m1 m();
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defparam Loop2[i].m.p = 1 + i;
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end
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for (i = 4; i < 6; i = i + 1) begin : Loop3
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m1 m();
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defparam m2.Loop3[i].m.p = 1 + i;
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end
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endgenerate
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reg failed = 0;
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initial begin
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$display("Loop1[0].m.p = %0d", Loop1[0].m.p);
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if (Loop1[0].m.p !== 1) failed = 1;
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$display("Loop1[1].m.p = %0d", Loop1[1].m.p);
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if (Loop1[1].m.p !== 2) failed = 1;
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$display("Loop2[2].m.p = %0d", Loop2[2].m.p);
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if (Loop2[2].m.p !== 3) failed = 1;
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$display("Loop2[3].m.p = %0d", Loop2[3].m.p);
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if (Loop2[3].m.p !== 4) failed = 1;
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$display("Loop3[4].m.p = %0d", Loop3[4].m.p);
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if (Loop3[4].m.p !== 5) failed = 1;
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$display("Loop3[5].m.p = %0d", Loop3[5].m.p);
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if (Loop3[5].m.p !== 6) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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