73 lines
1.8 KiB
Verilog
73 lines
1.8 KiB
Verilog
`begin_keywords "1364-2005"
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module top;
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reg pass;
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real rvar;
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wire [3:0] var;
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assign var = rvar;
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initial begin
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pass = 1'b1;
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rvar <= 1'b0;
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#1 rvar = 1'b1;
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#1 rvar = 2'b10;
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#1 rvar = 2'b11;
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#1 if (pass) $display("PASSED");
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end
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real_to_bit u1(rvar);
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real_to_real u2(rvar);
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real_to_real u3[1:0](rvar);
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real_to_vec u4(rvar);
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real_to_vec u5[1:0](rvar);
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bit_to_real u6(var[0]);
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vec_to_real u7(var);
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vec_to_real u8[1:0](var);
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endmodule
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// Check a real value going to a single bit.
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module real_to_bit (input wire in);
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always @(in) if (in !== $stime%2) begin
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$display("Failed real_to_bit %m at %1d, got %b, expected %2b",
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$stime, in, $stime%2);
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top.pass = 1'b0;
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end
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endmodule
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// Check a real value going to a real wire.
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module real_to_real (input wire real in);
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always @(in) if (in != $stime) begin
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$display("Failed real_to_real %m at %1d, got %0d, expected %0d",
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$stime, in, $stime);
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top.pass = 1'b0;
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end
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endmodule
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// Check a real value going to multiple bit.
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module real_to_vec (input wire [3:0] in);
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always @(in) if (in !== $stime) begin
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$display("Failed real_to_vec %m at %1d, got %0d, expected %0d",
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$stime, in, $stime);
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top.pass = 1'b0;
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end
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endmodule
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// Check a single bit going to a real wire.
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module bit_to_real (input wire real in);
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always @(in) if (in != $stime%2) begin
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$display("Failed bit_to_real %m at %1d, got %0d, expected %0d",
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$stime, in, $stime%2);
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top.pass = 1'b0;
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end
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endmodule
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// Check a vector going to a real wire.
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module vec_to_real (input wire real in);
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always @(in) if (in != $stime) begin
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$display("Failed vec_to_real %m at %1d, got %0d, expected %0d",
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$stime, in, $stime);
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top.pass = 1'b0;
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end
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endmodule
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`end_keywords
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