39 lines
693 B
Verilog
39 lines
693 B
Verilog
module test ();
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parameter p = 0;
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reg dummy;
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initial dummy = block.f(0);
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generate case(1)
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p==0:
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begin : block
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function f;
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input i;
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begin
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$display("p == 0: %0s", p==0?"OK":"FAILED");
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if (! (p==0)) $finish;
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end
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endfunction
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end
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default:
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begin : block
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function f;
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input i;
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begin
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$display("default: %0s", p!=0?"OK":"FAILED");
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if (p==0) $finish;
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end
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endfunction
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end
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endcase
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endgenerate
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endmodule
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module top ();
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test #(0) a();
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test #(1) b();
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initial #1 $display("PASSED");
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endmodule
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