77 lines
1.9 KiB
Verilog
77 lines
1.9 KiB
Verilog
`timescale 1us/100ns
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module top;
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reg pass = 1'b1;
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reg [3:0] ia = 4'd1;
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wire signed [3:0] iconstp, iconstm, isfunc, iufunc;
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wire [7:0] istring;
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/* Integer constant value. */
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assign #1 iconstp = 2; // 2
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assign #1 iconstm = -2; // -2
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assign #1 istring = "0"; // "0"
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/* Integer System Function. */
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assign #1 isfunc = $rtoi(2.0); // 2
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/* Integer User Function. */
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assign #1 iufunc = int_func(ia); // 2
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initial begin
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// $monitor($realtime,, iconstp,, iconstm,, istring,, iufunc,, isfunc);
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#0.9;
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if (iconstp !== 4'bx) begin
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pass = 1'b0;
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$display("Integer: constant (positive) value not delayed.");
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end
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if (iconstm !== 4'bx) begin
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pass = 1'b0;
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$display("Integer: constant (negative) value not delayed.");
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end
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if (istring !== 8'bx) begin
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pass = 1'b0;
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$display("Integer: string value not delayed.");
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end
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if (isfunc !== 4'bx) begin
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pass = 1'b0;
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$display("Integer: system function value not delayed.");
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end
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if (iufunc !== 4'bx) begin
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pass = 1'b0;
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$display("Integer: user function value not delayed.");
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end
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#0.1;
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#0;
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if (iconstp !== 2) begin
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pass = 1'b0;
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$display("Integer: constant (positive) value not delayed correctly.");
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end
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if (iconstm !== -2) begin
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pass = 1'b0;
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$display("Integer: constant (negative) value not delayed correctly.");
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end
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if (istring !== "0") begin
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pass = 1'b0;
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$display("Integer: string value not delayed correctly.");
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end
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if (isfunc !== 2) begin
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pass = 1'b0;
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$display("Integer: system function value not delayed correctly.");
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end
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if (iufunc !== 2) begin
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pass = 1'b0;
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$display("Integer: user function value not delayed correctly.");
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end
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if (pass) $display("PASSED");
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end
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function [31:0] int_func;
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input [31:0] in;
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int_func = in * 2;
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endfunction
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endmodule
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