30 lines
563 B
Verilog
30 lines
563 B
Verilog
module main;
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reg [23:20] foo;
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wire [3:0] test = {foo[22:20] == 3'd0, foo[22:20]};
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initial begin
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foo = 4'b1_000;
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#1 if (test !== 4'b1_000) begin
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$display("FAILED -- foo=%b, test=%b", foo, test);
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$finish;
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end
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foo = 4'b0_111;
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#1 if (test !== 4'b0_111) begin
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$display("FAILED -- foo=%b, test=%b", foo, test);
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$finish;
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end
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foo = 4'b0_000;
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#1 if (test !== 4'b1_000) begin
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$display("FAILED -- foo=%b, test=%b", foo, test);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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