mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-03 16:29:25 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
68 lines
871 B
Verilog
68 lines
871 B
Verilog
module lvl3;
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reg [1:0] m[1:0];
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initial begin
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fork: my_fork
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repeat (1) begin
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m[0] = 2'b0;
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end
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repeat (1) begin
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m[1] = 2'b1;
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end
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join
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end
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endmodule
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module lvl2_0;
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reg r;
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initial r = $random;
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lvl3 lvl3();
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endmodule
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module lvl1_0;
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reg r;
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function f_foo;
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input bar;
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begin
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f_foo = bar;
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end
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endfunction
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initial r = f_foo(r);
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lvl2_0 lvl2();
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endmodule
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module top0;
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reg r;
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task t_bar;
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r = 1'b0;
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endtask
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initial begin: my_init
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r = $random;
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t_bar;
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end
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lvl1_0 lvl1();
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endmodule
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module lvl2_1;
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integer i;
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initial i = $random;
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lvl3 lvl3();
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endmodule
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module lvl1_1;
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integer i;
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initial i = $random;
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lvl2_1 lvl2();
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endmodule
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module top1;
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integer i;
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initial i = $random;
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lvl1_1 lvl1();
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endmodule
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module top2;
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initial $test;
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endmodule
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