mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-09-01 10:16:40 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
18 lines
533 B
Verilog
18 lines
533 B
Verilog
//---------------------------------------------------------------------------
|
|
//
|
|
//---------------------------------------------------------------------------
|
|
module xor_try;
|
|
|
|
reg [1:0] inp_xor; // The two-bit inputs to the XOR
|
|
reg out_xor; // The XOR output
|
|
reg clk;
|
|
|
|
initial begin clk = 1'b1; $sn; #160 $finish(0); end
|
|
always #50 clk = ~clk;
|
|
// The clock
|
|
|
|
always @(posedge clk) out_xor = #1 (inp_xor[0] ^ inp_xor[1]);
|
|
// The actual operation
|
|
endmodule
|
|
|