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https://github.com/steveicarus/iverilog.git
synced 2026-09-01 18:26:23 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
19 lines
709 B
Verilog
19 lines
709 B
Verilog
module top;
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reg [80*8:1] simp_str, info_str;
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real ver, subver;
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initial begin
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ver = $simparam("simulatorVersion");
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subver = $simparam("simulatorSubversion");
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// For 0.9 only use one digit after the decimal point.
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if (ver < 1.0) $swrite(simp_str, "%0.1f.%0.0f", ver, subver);
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// For the rest, 10 and above, use no digits after the decimal point.
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else $swrite(simp_str, "%0.0f.%0.0f", ver, subver);
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$get_version(info_str);
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if (simp_str !== info_str) begin
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$display("FAILED");
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$display("$simparam version: '%0s'", simp_str);
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$display("vpi_get_vlog_info version: '%0s'", info_str);
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end else $display("The two versions matched!");
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end
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endmodule
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