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https://github.com/steveicarus/iverilog.git
synced 2026-09-07 11:51:38 +02:00
Stephen Williams
cea237b407
By adding ivtest to the iverilog source tree, it is easier to keep the regression test synchronized with the source that is being tested. This should be especially helpful for PRs that add a new feature, and have a matching ivtest PR with the regression test for that feature.
65 lines
1.0 KiB
Verilog
65 lines
1.0 KiB
Verilog
/*
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* A D-type flip-flop to check synchronous logic works
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* correctly.
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*/
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module testbench;
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reg d, clk, rst, enable;
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wire q, q_bar;
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dff uut(q, q_bar, d, clk, rst);
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initial clk <= 0;
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always @(clk)
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if (enable)
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#1 clk <= !clk;
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initial begin
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enable <= 1;
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rst <= 1;
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d <= 1'bx;
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#2;
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if (q !== 0)
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begin
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$display("FAILED -- Not reset");
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$finish;
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end
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rst <= 0;
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d <= 1'b1;
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#2;
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if (q !== 1)
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begin
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$display("FAILED -- q not 1 as expected");
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$finish;
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end
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d <= 1'b0;
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#2;
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if (q !== 0)
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begin
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$display("FAILED -- q not 0 as expected");
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$finish;
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end
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rst <= 1;
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#2;
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enable <= 0; // Alternative to using $finish
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$display("PASSED");
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end
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endmodule // testbench
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module dff(q, q_bar, d, clk, rst);
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output q, q_bar;
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input d, clk, rst;
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reg q;
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always @(posedge clk or posedge rst)
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if (rst)
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q <= 1'b0;
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else
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q <= d;
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not(q_bar, q);
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endmodule // dff
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